There are three types of caching algorithm measurements:
FIFO: First In First Out, *** First Out. Determines the stored time; data far from the current *** is prioritized for elimination.
LRU: Least Recently Used, *** Less Used. Determine the time when the most recent data is used; the data currently far away is prioritized and eliminated.
LFU: Least Frequently Used, *** Not used frequently. If data is used the least frequently within a certain period, it will be eliminated first.
FIFO Data Buffer:
FIFO (First Input First Output) is a type of ***First-out data cache. Data entered is read from the FIFO buffer first. Compared to RAM, there is no external read/write address line, making it simpler to use, but it can only write data sequentially. Sequential data readout is not like ordinary memory, where the address line determines whether to read or write to a specified address.
Functions of FIFO data caches:
FIFOs are generally used for data transmission between different clock domains. For example, one end of a FIFO is AD data acquisition, and the other end is the computer's PCI bus. Assuming its AD acquisition rate is 16 bits at 100Kbps, the data volume per second is 100K×16bit = 1.6Mbps, while the PCI bus speed is 33MHz and bus width is 32bit, resulting in a transmission rate of 1056Mbps. Between two different clock domains, FIFO can be used as a data buffer. Additionally, for data interfaces of different widths, FIFO can be used. For example, a microcontroller outputs 8-bit data, while a DSP may have 16-bit data input. When connecting the microcontroller to the DSP, FIFO can be used to achieve data matching.
FIFO data buffers are classified by operating clock domain:
Based on the FIFO operating clock domain, FIFOs can be divided into synchronous FIFOs and asynchronous FIFOs. Synchronous FIFO means that the read and write clocks are the same clock, and read and write operations occur simultaneously when the clock edges arrive; Asynchronous FIFO refers to inconsistent read and write clocks; the read and write clocks are independent of each other. There are generally two understandings of asynchronous FIFOs: one is that read/write operations do not use clocks but directly control wr_en (Write Enabled) and rd_en (Read Enabled); The other is that in FPGA and ASIC designs, asynchronous FIFOs have dual-port FIFOs with two clocks, where read operations are performed on their respective clock extensions, allowing read or write to be performed simultaneously under two different clocks. Asynchronous FIFOs use much more resources in FPGA design summaries than synchronous FIFOs, so synchronous FIFOs are preferred. However, for most peripheral interfaces within ARM systems, asynchronous FIFOs are used.
The kernel buffer of a network card is located in the PC's memory and controlled by the kernel, while the network card has a FIFO buffer or ring buffer, which should distinguish the two. Since the FIFO is relatively small, it tries to store data in the kernel buffer whenever possible.
The buffer in the network card does not belong to either the kernel space nor the user space. It is a hardware buffer that allows a buffer between the network card and the operating system;
The kernel buffer is in kernel space and memory, used for kernel programs, serving as a data buffer for reads or writes to hardware;
The user buffer is in user space and memory, used for user programs as a data buffer for reads or writes to hardware;
Additionally, to speed up data interaction, kernel buffers can be mapped to user space, allowing kernel and user programs to access this interval simultaneously.